kw.\*:("Plan masse")
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TCG-S: Orthogonal coupling of P*-admissible representations for general floorplansLIN, Jai-Ming; CHANG, Yao-Wen.Design automation conference. 2002, pp 842-847, isbn 1-58113-461-4, 6 p.Conference Paper
Logiciel f, outil informatique de conception solaire = f software, computer tool for solar design1984, 55 p.Report
Floorplanning with alignment and performance constraintsXIAOPING TANG; WONG, D. F.Design automation conference. 2002, pp 848-853, isbn 1-58113-461-4, 6 p.Conference Paper
Génération automatique de plans de masse = Automatic generation of layout plansKOUKA, E. F.TSI. Technique et science informatiques. 1989, Vol 8, Num 6, pp 557-569, issn 0752-4072, 13 p., no specArticle
Tightly integrated placement and routing for FPGAsKANNAN, Parivallal; BHATIA, Dinesh.Lecture notes in computer science. 2001, pp 233-242, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Impedance of a transverse slot in the ground plane of an offset striplineDAS, B. N; PRASAD, K. V. S. V. R.IEEE transactions on antennas and propagation. 1984, Vol 32, Num 11, pp 1245-1248, issn 0018-926XArticle
A new placement method for direct mapping into LUT-based FPGAsABKE, Joerg; BARKE, Erich.Lecture notes in computer science. 2001, pp 27-36, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Evaluateur topologique prédictif pour la génération automatique des plans de masse de circuits VLSI = Predictive topological evaluator for the automatic generation of VLSI circuit ground surfacesDA LUZ REIS, Ricardo Augusto.1983, 353 pThesis
High voltage microwave DC block for microstrip ground planesKOSCICA, T. E.Electronics Letters. 1990, Vol 26, Num 16, pp 1287-1288, issn 0013-5194Article
New clustering approach to chip floorplan using functional dataHARADA, I; ADACHI, T.Electronics Letters. 1987, Vol 23, Num 17, pp 900-902, issn 0013-5194Article
Enumerating floorplans with n roomsNAKANO, Shin-Ichi.Lecture notes in computer science. 2001, pp 107-115, issn 0302-9743, isbn 3-540-42985-9Conference Paper
EVALUATEUR TOPOLOGIQUE POUR CIRCUITS VLSI: MODULE D'EVALUATION DE ROM = TOPOLOGICAL EVALUATOR FOR VLSI CIRCUITS: ROM EVALUATION MODULEREIS RICARDO.1981; ; FRA; DA. 1981; IMAG-RR/252; 51 P.; 30 CM; ABS. ENG; BIBL. 1 P.;[RAPP. RECH.-LAB. INFORM. MATH. APPL. GRENOBLE; VOL. RR-252]Report
An Effective Overlap Removable Objective for Analytical Placement : Circuit, System, and Computer TechnologiesKUWABARA, Syota; KOHIRA, Yukihide; TAKASHIMA, Yasuhiro et al.IEICE transactions on fundamentals of electronics, communications and computer science. 2013, Vol 96, Num 6, pp 1348-1356, issn 0916-8508, 9 p.Article
A hierarchical approach for incremental floorplan based on genetic algorithmsYONGPAN LIU; HUAZHONG YANG; RONG LUO et al.Lecture notes in computer science. 2005, issn 0302-9743, isbn 3-540-28323-4, 3Vol, Part 3, 219-224Conference Paper
An antenna pattern measurement technique for eliminating the fields scattered from the edges of a finite ground planeWILLIAMS, J. T; DELGADO, H. J; LONG, S. A et al.IEEE transactions on antennas and propagation. 1990, Vol 38, Num 11, pp 1815-1822, issn 0018-926X, 8 p.Article
Analysis of stripline/slot transitionMUIR, A.Electronics Letters. 1990, Vol 26, Num 15, pp 1160-1162, issn 0013-5194Article
An analytical approach to floorplanning for hierarchical building blocks layoutCHANG-SHENG YING; JOSHUA SOOK-LEUNG WONG.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 4, pp 403-412, issn 0278-0070Article
Óbidos : Un complexe touristique haut en architecture = Óbidos: A tourist complex rich in architectureALBERT, Marie-Douce.Le Moniteur des travaux publics et du bâtiment. 2012, Num NOV, pp 30-31, issn 0026-9700, 2 p., NSArticle
Construction plan of Tohoku through lineKOBAYASHI, Chika.Japanese railway engineering. 2009, Vol 49, Num 1, issn 0448-8938, a, 11-13 [4 p.]Article
Usinf CAD in construction field engineeringABUDAYYEH, O; MALETIC, V.Advances in engineering software (1992). 1994, Vol 20, Num 1, pp 13-17, issn 0965-9978Article
Complex images of an electric dipole in homogeneous and layered dielectrics beween two ground planesYANG, J. J; CHOW, Y. L; HOWARD, G. E et al.IEEE transactions on microwave theory and techniques. 1992, Vol 40, Num 3, pp 595-600, issn 0018-9480Article
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generationBAR-YEHUDA, R; FELDMAN, J. A; PINTER, R. Y et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 7, pp 737-743, issn 0278-0070Article
Mismatch simulation for layout sensitive parameters of IC components and devicesTRÖSTER, G; TOMASZEWSKI, P.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 2, pp 101-107, issn 0278-0070Article
Algorithms for physical design of sea-of-gates chipsSHRAGOWITZ, E; LEE, J; SAHNI, S et al.Computer-aided design. 1988, Vol 20, Num 7, pp 382-397, issn 0010-4485Article
Canonical decomposition, realizer, Schnyder labeling and orderly spanning trees of plane graphs: (Extended abstract)MIURA, Kazuyuki; AZUMA, Machiko; NISHIZEKI, Takao et al.Lecture notes in computer science. 2004, pp 309-318, issn 0302-9743, isbn 3-540-22856-X, 10 p.Conference Paper